The present invention relates to data processing systems and, more particularly, to a delay line used in such systems wherein the delay line has reduced data glitches.
Passive delay lines are commonly used in data processing systems in order to generate, shape and sequence various clocking, timing and other signals. Often a single, principal timing signal will be provided to one or more delay lines in order to generate a group of timing signals used throughout the system. Such delay lines commonly have an input and a number of output taps, with inductors and capacitors separating the taps in order provide a different amount of delay (relative to the input signal) in the output signal at each output tap.
A significant problem associated with delay lines is the electrical noise that they sometimes generate. This noise leads to glitches and errors in the data that is being processed in the data processing system.
One source of the noise in a delay line is the signal reflections caused by the capacitance of the load at each output tap. These reflections arise because of the transmission line characteristics of the signal path in the delay line. As is known to those familiar with transmission line theory, signal reflections will arise in a transmission line from discontinuities in the line. Generally, a signal will travel down a transmission line without being reflected as long as the characteristic impedance of the line remains uniform. In this context, the "characteristic impedance" is the impedance that the signal "sees" in front of it at any instant as it travels down the line. At the moment that the signal sees a discontinuity in the line (a variance from the otherwise uniform characteristic impedance), a signal is reflected back since the signal, at least momentarily, experiences a different impedance and there is a change in the voltage level of the signal in the line at the discontinuity. In a passive delay line of the type described above, a discontinuity will exist at each output tap where there is a load.
In the past, transmission line discontinuities at the output taps of a passive delay line were not viewed as a major problem, since the resulting signal reflections tended to be relatively small. As the physical size of integrated circuit chips that provide processing and memory functions in data processing systems has decreased, however, there has been a tendency to also decrease the amount of space required for other circuits, such as delay lines, by reducing the number of the delay lines used in the system. As a result, more loads are attached to fewer delay lines and, as multiple loads are attached to individual output taps of a delay line, the capacitance at each of those taps increases. The increased capacitance results in greater discontinuities on the signal path in the delay line and, hence, larger reflections and more glitches in the system.